Generally, semiconductor integrated circuits for which high reliability is required are subjected to in-depth failure inspection before shipping, and only those that are ensured for normal operation are used in products. However, even those semiconductor integrated circuits may fail after shipping due to deterioration with age, or the like.
A conventional technique described in Patent Document 1 is a method for detecting a failure of a semiconductor integrated circuit due to deterioration with age, or the like. With this technique, separately from a logic circuit that is provided in the semiconductor integrated circuit and subjected to failure inspection, another logic circuit of the same configuration is provided as a mirror circuit, and the outputs of these logic circuits are compared with each other, determining that there is an error when the outputs differ from each other. The failure detection method is called a “mirror circuit method”.
Patent Document 1: Japanese Laid-Open Patent Publication No. 11-305991